1. Field of the Invention
The present invention relates to an image display controller adapted for use in a computer graphic apparatus or the like.
2. Description of the Prior Art
FIG. 3 is a block diagram showing an exemplary structure of a conventional image display controller capable of performing a multi-window display operation which superimposes a plurality of window images on a predetermined overlay image.
An overlay plane memory 1 serves to store overlay image data (basic data) forming the overlay on a screen, and RGB plane memories 5, 6 serve to store window image data. Meanwhile a window ID plane memory 4 is used for storing window identification data indicative of a window setting range.
For example, when images of five windows W1 through W5 are superimposed on one overlay image as illustrated in FIG. 4A, 4-bit basic data of the overlay image alone is written in the overlay plane memory 1 as shown in FIG. 4C. The overlay image includes, in addition to a rhombic pattern, some other display relative to command data required for control of an icon and so forth. Although the display relative to the command data may also be regarded as a window image, it is assumed here for the sake of descriptive convenience that any image written in the overlay plane memory 1 is defined as an overlay image, and any image written in the RGB plane memories 5, 6 is defined as a window image. Each window portion of the overlay plane memory 1 is rendered substantially blank so that the window image can be displayed there as it is.
The image data being presently displayed within the windows W1, W4, W5 as shown in FIG. 4D for example are stored in the RGB plane memory 5, and the image data to be displayed next are stored in the windows W2, W3. The image data being presently displayed within the windows W2, W3 as shown in FIG. 4E for example are stored in the RGB plane memory 6, and the image data to be displayed next are stored in the windows W1, W4, W5. Each of such image data regarding R (red), G (green) and B (blue) is composed of 8 bits.
Meanwhile in the window ID plane memory 4, as shown in FIG. 4B, 4-bit window ID 1 (0001) through (0101) are recorded in the areas of the windows W1 through W5 to signify that such are the areas of the windows W1 through W5. And in the overlay area, ID 0 (0000) is recorded to signify that the relevant area is not the one of any window.
The R, G, B outputs of the RGB plane memories 5 and 6 are supplied respectively to the contacts of switches 7R, 7G, 7B. And the output of the overlay plane memory 1 is supplied to a lookup table (LUT) 2, where the 4-bit basic data are converted into substantial R, G, B image data each composed of 8 bits. Thus the image data of the RGB plane memories 5 and 6 are composed of 24 bits (24 planes) and can be displayed in 16,700,000 (=2.sup.24) colors, whereas the image data (basic data) of the overlay plane memory 1 is composed of 4 bits (4 planes) and is consequently displayed merely in 16 (=2.sup.4) colors. The above arrangement is grounded on the reason that the overlay image generally does not require so many kinds of colors, and therefore the number of bits is reduced to diminish the memory capacity.
The R, G, B outputs of the LUT 2 are supplied respectively to the contacts of the switches 7R, 7G, 7B.
The switches 7 (7R, 7G, 7B) are selectively changed by the output of the LUT 3, so that either the overlay image data written in the overlay plane memory 1 or the window image data written in the RGB plane memory 5 or 6 is selected and outputted to be displayed on an unshown CRT or the like.
For controlling such selective change of the switches 7, the window identification data is read out from the window ID plane memory 4 and then is inputted to the LUT 3. As shown in FIG. 4B, the window identification data is so arranged as to correspond to the windows W1 through W5. And in response to the input identification data (0 in the embodiment) representing the overlay image (not any window), the switches 7 are changed in a manner to select the output of the LUT 2. On the other hand, in response to the input window identification data (1 through 5 in the embodiment) representing the windows W1 through W5, the switches 7 are so changed as to select the output of the RGB plane memory 5 or 6. Selection of either the RGB plane memory 5 or 6 is controlled through rewriting the content of the LUT 3 by the CPU 13. In this case, the switches 7 are changed in such a manner as to select the output of the RGB plane memory 5 in response to the window identification data of the windows W1, W4, W5, or to select the output of the RGB plane memory 6 in response to the window identification data of the windows W2, W3.
Thus, the window images illustrated in FIG. 4A are displayed in accordance with the outputs of the switches 7.
The read addresses in the overlay plane memory 1, the window ID plane memory 4 and the RGB plane memories 5, 6 are controlled by the output of a read address generator 8 inputted to each memory via an address bus.
Now a data writing operation will be described below.
The window identification data inputted via a data bus is written in the window ID plane memory 4, and the overlay image data inputted via the data bus is written in the overlay plane memory 1.
In the RGB plane memories 5, 6 are written the window image data inputted via the data bus, and such writing operation is controlled in the following manner.
In the RGB plane memory 5 for example, it is necessary to record only the image data of the windows W1, W4, W5 as illustrated in FIG. 4D. Therefore, the memory selector 11 is so actuated as to render the RGB plane memory 5 ready for writing the data under control of the CPU 13. The RGB plane memory 5 (as any of the RGB plane memory 6, overlay plane memory 1 and window ID plane memory 4) has a read-only port for display, and another port for enabling the CPU 13 to write or read the data therethrough, wherein the operations can be performed simultaneously in both ports.
When the image data for the window W1 is written, the ID generator 12 outputs window ID 1 to a comparator 10, which also receives the window identification data of FIG. 4B from the window ID plane memory 4. The comparator 10 compares the two input data with each other per pixel and, upon coincidence of the two inputs, supplies a signal to the RGB plane memory 5 for recording the relevant pixel, whereby the image data is written in the area of the window W1 in the RGB plane memory 5.
When the image data for the window W4 or W5 is written, the ID generator 12 outputs window ID 4 or 5. Then such image data is recorded in the window 4 or 5.
The same procedure is executed in the case of writing the window image data in the RGB plane memory 6.
The write addresses in the memories 1, 4, 5, 6 are controlled by the output of a write address generator 9.
For displaying three-dimensional graphics as window images, there are further provided a Z buffer memory 14, a Z comparator 15, a Z value generator 16, a logic circuit 17 and a pattern generator 18.
In the Z buffer memory 14 for storing the depth data of display images, the greatest value is written first. For example, in case the Z buffer memory 14 has a 16-bit depth relative to each pixel, a value 65535 (=2.sup.16 -1) is set as the data for each pixel. The Z value generator 16 is controlled by the CPU 13 to generate the depth data (Z value) of the image to be written in the RGB plane memory 5 or 6. The depth data is so determined that the minimum Z value indicates the nearest image while the-maximum Z value indicates the farthest image. The Z comparator 15 compares the output of the Z buffer memory 14 with the output (Z value) of the Z value generator 16 per pixel, and when the Z value is smaller, the image data relevant thereto is written in the RGB plane memory 5 or 6 while such Z value is written at the relevant pixel position in the Z buffer memory 14. In case the Z value is equal to or greater than the output of the Z buffer memory 14, the image data relevant to such pixel is not written in the RGB plane memory 5 or 6. Also the Z value is not written either in the Z buffer memory 14.
If the data is overwritten in the RGB plane memory 5, 6 or the Z buffer memory 14, it follows that the new data is left therein. Accordingly, with repetition of the operation described above, the nearer image data (of the smaller Z value) is left in place of the farther image data (of the greater Z value), so that the image data of the greater depth is written in the RGB plane memory 5 or 6 and then is displayed.
The logic circuit 17 calculates the logic product (AND) of the output of the Z comparator 15 and that of the comparator 10, and supplies a write control signal to the RGB plane memory 5 or 6 in accordance with the result of such calculation. Therefore, three-dimensional graphics are drawn merely within the windows.
The pattern generator 18 is controlled by the CPU 13 and generates logic data 1 or 0 corresponding to a predetermined pattern. The logic circuit 17 further calculates the logic product (AND) of the pattern data, which is outputted from the pattern generator 18, and the output of the Z comparator 15, whereby three-dimensional graphics are drawn in the pattern-designated range within the window.
The calculation executed by the logic circuit 17 may be so modified that a variety of images are displayed by replacing a logic product (AND) with a logic sum (OR) or by properly combining predetermined outputs with each other.
As described above, in the conventional image display controller where the overlay plane memory 1 and the window ID plane memory 4 are independent of each other, there arises a problem of disordered display unless a timing coincidence is attained between the two memories in both the writing and reading operations. In addition, the number of windows displayable independently is limited by the number of window ID planes (16(=2.sup.4) in the above example) to consequently lower the efficiency of using the memories.